Formation of via holes is one of the important processes during the manufacture of a display panel. Through the via holes, electrical connections between circuit patterns located in different layer levels can be established. For example, in one of typical structures for an array substrate, a gate insulating layer covers gate lines; metallic layers, such as active layer, data lines, source electrode and drain electrode are formed on the gate insulating layer and are covered with a passivation layer; a drain electrode via hole is formed in the passivation layer on the drain electrode, so as to connect a pixel electrode with the drain electrode through the drain electrode via hole; and a gate connection via hole and a data connection via hole are formed over the gate lines and the data lines, respectively, so as to expose the gate lines and the data lines to be connected with a driving line.
The drain electrode via hole and the data connection via hole are formed by etching the passivation layer; and the gate connection via hole is formed by etching the passivation layer and the gate insulating layer. In a conventional technology, the drain electrode via hole, the data connection via hole and the gate connection via hole are usually formed by a one-step etching process. However, different film layers usually have different etching rates, and a ratio between etching rates in different film layers is defined as a selection ratio. When etching the gate insulating layer to form a gate connection via hole after forming a drain electrode via hole and a data connection via hole by etching process, it is accompanied with an etching of the metallic layers that form the drain electrode and data lines. If a selection ratio is defined as an etching rate for the gate insulating layer/an etching rate for the metallic layer, the selection ratio is preferably as larger as possible so that the metallic layer is less impacted when etching the gate insulating layer upon etching off the passivation layer.
Moreover, at present, a liquid crystal display (LCD) panel with narrow bezel has become one of the important development trends. For a panel design of relatively narrow bezel, a precision level of original equipments has to be considered, and if the original equipments cannot meet the required precision level, the realizability of the process as utilized must be taken into account. A via hole with reduced size is just a direct optimizing process in developing a product with a narrow bezel, because given a certain line width, the smaller the via hole is, the more precise the wiring is. A smaller via hole requires a larger slope angle, which, however, needs a smaller selection ratio between the gate insulating layer and the metallic layer. Since the one-step etching process cannot flexibly set etching conditions according to the slope angle and the selection ratio as required due to its fixed etching conditions, it's difficult to meet both of the above criteria.